STT-MRAM (spin torque transfer magneto-resistive magnetic random-access memory) is a promising candidate for next generation nonvolatile memory. A STT-MRAM comprises a plurality of MRAM cells. A MRAM cell 100, as depicted in FIG. 1, comprises a tunnel magneto-resistance device (TMR for short hereafter) 110 for storing a data, and an enabling NMOS (n-channel metal oxide semiconductor) switch 120 for enabling an access to TMR 110. The enabling NMOS switch 120 is controlled by a word line (WL); when WL is high, TMR 110 can be accessed via a bit line (BL) and a source line (SL). TMR 110 comprises: a ferromagnetic free layer 113, an insulating barrier layer 112, and a ferromagnetic fixed layer 111. The ferromagnetic fixed layer 111 is magnetized to a fixed orientation, while the ferromagnetic free layer 113 is magnetized to an orientation either parallel or anti-parallel to the orientation of the ferromagnetic fixed layer 111, depending on the data stored in TMR 110. If binary “1” is stored, TMR 110 is in an anti-parallel state and electrically behaves as a resistor of a high resistance. If binary “0” is stored, TMR 110 is in a parallel state and electrically behaves as a resistor of a low resistance. The resistance of TMR 110, either high or low, is a function of an electrical current flowing through it. A typical transfer characteristics 200 between the electrical current (with polarity defined in accordance with the direction flowing from BL to SL; i.e., the electrical current is said to be negative if it flows from SL to BL) and the resistance of TMR 110 are depicted in FIG. 2. As shown, TMR 110 exhibits a high resistance when it is in the anti-parallel state and a low resistance when it is in the parallel state. However, TMR 110 can stay in the anti-parallel (i.e. high resistance) state only if the electrical current is below a 1st threshold (which is positive); when the electrical current is positive and above the 1st threshold, TMR 110 will be programmed to (i.e., written into) the parallel state, as indicated by REGION I, even if it is previously in the anti-parallel state. Likewise, TMR 110 can stay in the parallel (i.e. low resistance) state only if the electrical current is above a 2nd threshold (which is negative); if the electrical current is negative and below the 2nd threshold, the TMR will be programmed to (i.e., written into) the anti-parallel state, as indicated by REGION III, even if it is previously in the parallel state. Based on the transfer characteristics 200, one can figure out methods to write to and read from TMR 110. To write a binary “0” data into TMR 110, one needs make it enter REGION I by applying a positive electrical current (flowing from BL to SL) above the 1st threshold (i.e. more positive than the 1st threshold); to write a binary “1” data into TMR 110, one needs to make it enter REGION III by applying a negative electrical current (i.e. flowing from SL to BL) below the 2nd threshold (i.e. more negative than the 2nd threshold). To read the data stored in TMR 110, one needs to make it stay in REGION II by applying an electrical current between the 2nd threshold and the 1st threshold (i.e., no more positive than the 1st threshold and also no more negative than the 2nd threshold); this electrical current will cause a voltage difference between BL and SL; and the voltage difference depends on the state of TMR 110: the voltage difference is larger if TMR 110 is in the anti-parallel state, and smaller otherwise. One then compares the voltage difference between BL and SL with a reference voltage. If the voltage difference is larger than the reference voltage, TMR 110 is detected to be in the anti-parallel state and the data stored is deemed binary “1”; if the voltage difference is smaller than the reference voltage, TMR 110 is detected to be in the parallel state and the data stored is deemed binary “0.” It is not easy, however, to establish a reliable reference voltage for the read operation, because the resistance of a TMR, either high or low, is temperature dependent, and so is the voltage difference between BL and SL.
Conventional systems may include a STT-MRAM circuitry that includes a write circuit and a read circuit. In the read circuit, the reference voltage for the read operation is established by using a NMOS (n-channel metal-oxide semiconductor) transistor, the resistance of which is controlled by a voltage, to mimic a resistor of resistance that is lower than the high resistance (when the TMR is in the anti-parallel state) but higher than the low resistance (when the TMR is in the parallel state) over the entire temperature range of interest. This arrangement, however, does not lead to optimal performance for all temperatures. In the write circuit, a bi-directional driver may be used; the circuit, however, is quite complex.